In a conventional wafer level package process, package structures are directly formed on a wafer which has circuits formed thereon by rerouting the wafer, coating the wafer with dielectric material, and attaching solder balls to the wafer. The conventional wafer level package process is only suitable for the circuits with larger size and less input/output devices. In detail, because the solder balls need to connect with contact areas of the circuit board, the pitch space of the circuit should be larger than 0.25 mm based on current design rule. Therefore, the conventional solder ball process is not suitable for the small-size integrated circuit devices which are incapable of providing enough pitch space.
The post-packaging process has been used to increase the available contact areas of the integrated circuit devices. For example, the packaged integrated circuit devices are cut into individual dies (chips) and then moved to a larger substrate. Next, the post-packaging process is performed on the larger substrate to form additional contact lines for the integrated circuit devices, whereby the contact areas of the integrated circuit devices can be increased. This conventional post-packaging process suffers from high process complexity and cost, and therefore, it is desired to have a novel package structure for intergraded circuit devices and a method of the same to resolve the above-mentioned problems.